Processor features

                                                               Processor features

1.      SMM (System Management Mode)

SMM is a power management circuitry. This circuitry enables processors to conserve energy use and lengthen battery life. This was introduced initially in the Intel 486SL processor. SMM circuitry is integrated into the physical chip but operates independently to control the processor’s power use based on its activity level. It enables the user to specify time intervals after after which the CPU will be partially or fully powered down. It also supports the suspend/resume feature that allows for instant power on and power off, used mostly with laptop PCs. These settings are typically controlled via system BIOS settings.

While initially used mainly for power management, SMM was designed to be used by any low-level system functions that need to function independent of the OS and other software on the system. In modern system, this includes the following:

§  ACPI and APM power management functions

§  USB boot

§  Password and security functions

§  Thermal monitoring

§  Fan speed monitoring

§  BIOS updating

§  Wake on alert functions such as Wake on LAN (WOL)

2.      Superscalar Execution

The fifth generation Pentium and newer processors feature multiple internal instruction execution pipelines, which enable them to execute multiple instructions at the same time. The 486 and all preceding chips can perform only a single instruction at a time. Intel calls the capability to execute more than one instruction at a time superscalar technology. This technology provides additional performance compared with the 486.

The Pentium is one of the first Complex instruction set computer (CISC) chip to be considered superscalar.

3.      MMX technology

MMX technology was originally named for multimedia extensions, or matrix math extensions. MMX technology was introduced in the later fifth-generation Pentium processors as a kind of add-on that improves video compression/decompression, image manipulation, encryption, and I/O processing- all of which are used in a variety of today’s software. MMX consists of two main processor architectural improvements. The first is, all MMX chips have a larger internal L1 cache than non-MMX counterparts. The other part of MMX is that it extends the processor instruction set with 57 new commands or instructions, as well as new instruction capability called single instruction, multiple data (SIMD). SIMD enables one instruction to perform the same function on multiple pieces of data, similar to a teacher telling an entire class to “sit down”, rather than addressing each student one at a time. SIMD enables the chip to reduce processor-intensive loops common with video, audio, graphics, and animation.

The main drawbacks to MMX were that it worked only on integer values and used the floating-point unit for processing, so time was lost when a shift to floating-point operations was necessary.

4.      SSE, SSE2, SSE3 and SSSE3

Intel introduced the Pentium III processor and included in that processor an update to MMX called streaming SIMD Extensions (SSE). SSE includes 70 new instructions for graphics and sound processing over what MMX provided. The SSE instructions allow for floating-point calculations and now use a separate unit within the processor instead of sharing the standard floating-point unit as MMX did. SSE2 was introduced along with the Pentium 4 processor, and adds 144 additional SIMD instructions. SSE3 was introduced along with Pentium 4 Prescott processor, and adds 13 new SIMD instructions to improve complex math, graphics, video encoding, and thread synchronization. SSSE3 was introduced in the Xeon 5100 series server processors and in Core 2 processors. SSSE3 adds 32 new SIMD instructions.

Some of the technologies that benefit from the SSE include advanced imaging, 3D video, streaming audio and video (DVD playback), and speech-recognition applications. The benefits of SSE include the following:

§  Higher resolution and higher quality image viewing and manipulation for graphics software.

§  High- quality audio, MPEG2 video, and simultaneous MPEG2 encoding and decoding for multimedia applications.

§  Reduced CPU utilization for speech recognition, as well as higher accuracy and faster response times when running speech-recognition software.

5.      3DNow! , Enhanced 3DNow! , and Professional 3DNow!

3DNow! Technology was originally introduced as AMD’s alternative to the SSE instructions in the Intel processors. 3DNow! and Enhanced 3DNow! are sets of instructions that extend the multimedia capabilities of the AMD chips. This enables greater performance for 3D graphics, multimedia, and other floating point intensive PC applications. 3DNow! technology is a set of 21 instructions that uses SIMD techniques to operate on  arrays of data rather than single elements.

6.      Dynamic Execution

Dynamic execution enables the processor to execute more instructions on parallel, so tasks are completed more quickly. This technology innovation is composed of three main elements:

§  Multiple branch prediction- Predicts the flow of the program through several branches

§  Dataflow analysis- Schedules instructions to be executed when ready, independent of their order in the original program

§  Speculative execution- Increases the rate of execution by looking ahead of the program counter and executing instructions that are likely to be necessary

Branch Prediction

It enables the processor to keep the instruction pipeline full while running at a high rate of speed. A special fetch/decode unit in the processor uses a highly optimized branch-prediction algorithm to predict the direction and outcome of the instructions being executed through multiple levels of branches, calls and returns. By predicting the instructions outcome in advance, the instructions can be executed with no waiting.

Dataflow Analysis

Dataflow analysis studies the flow of data through the processor to detect any opportunities for out-of-order instruction execution. A special dispatch/execute unit in the processor monitors many instructions and can execute these instructions in an order that optimizes the use of multiple superscalar execution units. The resulting out-of-order execution of instructions can keep the execution units busy even when cache misses and other data-dependent instructions might otherwise hold things up.

Speculative Execution

Speculative execution is the processor’s capability to execute instructions in advance of the actual program counter. The processor’s dispatch/execute unit uses dataflow analysis to execute all available instructions in the instruction pool and store the results in temporary registers. A retirement unit then searches the instruction pool for completed instructions that are no longer data dependent on other instructions. If any such completed instructions are found, the results are committed to memory by the retirement unit.  

7.      Dual Independent Bus Architecture

DIB was created to improve processor bus bandwidth and performance. Having two (dual) independent data I/O buses enables the processor to access data from either of its buses simultaneously and in parallel, rather than in a singular sequential manner (as in single bus system). The main (often called front-side) processor bus is the interface between the processor and the motherboard or chipset. The second (back-side) bus in a processor with DIB is used for the L2 cache, enabling it to run at much greater speeds than if it were to share the main processor bus.

Two buses make up the DIB architecture: the L2 cache bus and the main CPU bus, often called FSB (front side bus). The dual bus architecture enables the L2 cache of the newer processors to run at full speed inside the processor core on an independent bus, leaving the main CPU bus (FSB) to handle normal data flowing in and out of the chip. The two buses run at different speed. The FSB is coupled to the speed of motherboard, whereas the back-side bus is coupled to the speed of the processor core.

8.      Hyper-Threading Technology

Intel’s Hyper-Threading (HT) technology allows a single processor two handle two independent sets of instructions at the same time. In essence HT technology converts a single physical processor into two virtual processors. Intel originally introduced HT-technology in its line of Xeon processors for servers. HT technology is also present in all Pentium 4 processors as well as the Pentium 4 Extreme edition.

Hyper-Threading Requirements

§  A compatible motherboard (chipset)

§  BIOS support to enable/disable HT technology

§  A compatible operating system such as Windows XP or Vista

9.                  Multicore Technology

 A multicore processor contains two or more processor cores in a single processor package. From outward appearances it still looks like a single processor, but inside there can be two, four, or even more processor cores. For example a dual-core processor contains two cores, and a quad-core processor contains four cores. Also, a dual-core processor uses slightly less power than two coupled single-core processors, principally because of the decreased power required to drive signals external to the chip. Furthermore, the cores share some circuitry, like the L2 cache and the interface to the front-side bus (FSB). Multi-core chips also allow higher performance at lower energy. This can be a big factor in mobile devices that operate on batteries. Since each core in a multi-core CPU is generally more energy-efficient, the chip becomes more efficient than having a single large monolithic core.